A Three-Dimensional DRAM Using Floating Body Capacitance Cells in an FD-SOI Process

This paper describes a three-dimensional DRAM in which the floating body capacitance (FBC) of a fully depleted SOI (FD-SOI) device is used as a storage node. This 1T DRAM lends itself particularly well to a 3D waferto-wafer bonding process because of the absence of deep etched and filled trench capacitor structure, and the improved thickness control tolerance in wafer thinning. A novel three-tier, 3D, 1T embedded DRAM is presented that can be vertically integrated with a microprocessor, achieving low cost, high-density on-chip main memory. A 394 Kbits test chip has been designed and fabricated using the Lincoln Labs 3-Tier 3D 0.18 um fully depleted SOI CMOS process where an earlier (and previously reported) successful 3D SRAM was obtained. The measured retention time under holding conditions in this 180 nm process is greater than 10 ms. The test chip measures an access time of 50 ns and operates at 10 MHz.